Biography

Currently a research engineer at Inria, I am interested in the impact of abstraction barriers (software/mathematics, hardware/software) on the security of computing systems.

Physical attacks (side-channels and fault injection) are the most obvious manifestations of this impact.

In the LHS lab, our physical attack benches allow us to exhibit vulnerabilities that are not achievable with software only.

Microarchitectural security is my second research axis, where I try to conciliate better core performance and security.

2024

• Generic SCARE: reverse engineering without knowing the algorithm nor the machine in JCEN

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• Characterizing and Modeling Synchronous Clock-Glitch Fault Injection in COSADE2024

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• La sécurité des abstractions en informatique in Cours AHP

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2021

• Under the dome: preventing hardware timing information leakage in CARDIS2021

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• Electromagnetic fault injection against a complex CPU, toward new micro-architectural fault models in JCEN2021

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2020

• Recommendations for a radically secure ISA in CARRV2020

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2019

• A case against indirect jumps for secure programs in SSPREW2019

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• Electromagnetic fault injection against a System-on-Chip, toward new micro-architectural fault models in arXiv:1910.11566

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2018

• Hardware-Assisted Program Execution Integrity: HAPEI in NordSec2018

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• When fault injection collides with hardware complexity in FPS2018

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• Let’s shock our IoT’s heart: ARMv7-M under (fault) attacks in ARES2018

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• Vérifier un code PIN in MISC97

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• Attaques par fautes in MISC96

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2017

• How TrustZone could be bypassed: Side-Channel Attacks on a modern System-on-Chip in WISTP2017

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2016

• A Multi-Round Side Channel Attack on AES using Belief Propagation in FPS2016

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• High-performance Elliptic Curve Cryptography by Using the CIOS Method for Modular Multiplication in CRiSIS2016

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• A template attack against VERIFY PIN algorithms in SECRYPT2016

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2014

• On the security of pairing implementations in PhD Thesis

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• Practical Validation of Several Fault Attacks against the Miller Algorithm in FDTC2014

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2013

• Inverting the Final Exponentiation of Tate Pairings on Ordinary Elliptic Curves Using Faults in CHES2013

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2012

• A DFA on AES based on the entropy of error distributions in FDTC2012

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2021

• Can we solve timing side-channels in the CPU ?

  Mon, Sep 13, 2021, TASER

• Timesecbench: Évaluation des fuites d’information par dépendances temporelles dans la microarchitecture

  Wed, Sep 8, 2021, FIC

• Timesecbench: a work in progress benchmark suite to assess microarchitectural timing leakages

  Wed, Apr 14, 2021, RISC-V Security Forum

2020

• Radically secure computing

  Tue, Feb 18, 2020, Séminaire Sécurité à l’Interface Logiciel/Matériel

2019

• Why there is no silver bullet to solve our security issues

  Tue, Nov 12, 2019, ENS Rennes seminar

• Electromagnetic fault injection against a System-on-Chip

  Wed, Oct 16, 2019, PHISIC2019

• How modern System-on-Chips are vulnerable to fault attacks

  Thu, May 23, 2019, JAIF2019

• Do Not Trust Modern System-on-Chips

  Fri, May 10, 2019, Séminaire Sécurité des Systèmes Électroniques Embarqués

2017

• Fault Injection Attacks

  Tue, Sep 19, 2017, CRiSIS 2017

• Fault Injection

  Fri, Jul 21, 2017, ISSISP 2017 - Summer school

• ronan.lashermes@inria.fr
• +33 (0)2 99 84 72 84
• 263 Avenue du Général Leclerc, 35042 Rennes