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Ronan Lashermes
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Timesecbench: a work in progress benchmark suite to assess microarchitectural timing leakages
Date
Wed, Apr 14, 2021
Event
RISC-V Security Forum
Location
Online
Links
Slides
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Radically secure computing
Timesecbench: Évaluation des fuites d’information par dépendances temporelles dans la microarchitecture
→