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Ronan Lashermes
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Timesecbench: Évaluation des fuites d’information par dépendances temporelles dans la microarchitecture
Date
Wed, Sep 8, 2021
Event
FIC
Location
Online
Links
Slides
←
Timesecbench: a work in progress benchmark suite to assess microarchitectural timing leakages
Can we solve timing side-channels in the CPU ?
→